Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point

In this work, we provide energy-efficient architectural support for floating point accuracy. Our goal is to provide accuracy that is far greater than that provided by the processor’s hardware floating point unit (FPU). Specifically, for each floating point addition performed, we “recycle” that operation’s error: the difference between the finite-precision result produced by the hardware and the result that would have been produced by an infinite-precision FPU. We make this error architecturally visible such that it can be used, if desired, by software. Experimental results on physical hardware show that software that exploits architecturally recycled error bits can achieve accuracy comparable to a 2Bbit FPU with performance and energy that are comparable to a B-bit FPU.